Electrical Stability of Low - K Polyimide / Teos Interface Alvin

The effect of lowK polymer passivation on electrical leakage was investigated to evaluate the reliability of polymer integration on device wafers. Polyimide passivation over Al(0.5%Cu) interconnects inlaid in TEOS increases the intralevel leakage current mainly along the polyimide/ TEOS interface. Moisture absorbed in the polyimide, as confirmed by residual gas analysis, further increases the interfacial as well as bulk leakages. These findings emphasize the importance of separating interconnects from direct contact with polyimide/TEOS interfaces and minimizing moisture content of polyimide during processing to ensure electrical isolation in multilevel interconnect architecture that employs lowK polymer dielectrics. INTRODUCTION Fluorinated polyimide could potentially replace TEOS as an interlevel dielectric in future interconnect technologies [1]. The capacitance reduction attained from integrating a low dielectric constant (lowK ) polymer offers benefits of reduced dynamic power dissipation, crosstalk, and signal propagation delay [2]-[4]. Although the thermal and mechanical properties of fluorinated polyimide have been characterized extensively [4]-[6], little has been reported on the electrical reliability associated with polymer integration on device wafers. Specifically, the electrical stability of the polymer/TEOS interface must be examined since both RIE and inlaid metal architectures incorporating lowK polymer dielectrics will likely employ inorganic dielectric liners as polymer capping layers, etch/polish stops, and/or hard masks [7], [8]. In this paper, we report increased line-to-line leakage along the interface between fluorinated polyimide and TEOS as a potential isolation issue. We also address the impact of moisture on the leakage since moisture management is critical for successful polyimide integration [9]. EXPERIMENT Fabrication of Test Structures Interdigitated inlaid Al(0.5%Cu) comb1 / serpentine / comb2 structures, as illustrated in Figure 1, were fabricated for intralevel leakage current measurements. The processing sequence commenced with a 68-Å gate oxidation on 10Ω •cm n-Si substrates followed by a 1.6-μm plasmaAdvanced Metallization and Interconnect Systems for ULSI Applications in 1997, San Diego, CA, October 1, 1997. 2 Loke et al. : Electrical Stability of LowK Polyimide/TEOS Interface enhanced TEOS deposition. Subsequent to the backside oxide etch, the TEOS surface was patterned to time-etch 0.5-μm deep trenches. The resulting trenches were filled by conformal Al(0.5%Cu) using a process sequence consisting of 200 Å PVD Ti, 0.1 μm collimated PVD Al, 0.8 μm CVD Al (DMAH precursor), and 0.6 μm PVD Al(1%Cu) [10]. The excess metal was immediately removed by chemo-mechanical polishing (CMP), resulting in planarized inlaid metal lines with equal line width and spacing of 0.5 μm, and a serpentine length of 1.7 m. The inlaid metal wafers comprised three experimental splits. In the first split [Figure 2(a)], a DuPont VM651 adhesion promoter was applied and 1.2 μm DuPont FPI-136M fluorinated polyimide ( K out-of-plane = 2.6 and K in-plane = 3.0 [11]) was subsequently spun over the inlaid lines, cured at 400 °C for 30 min, and capped by a 0.18-μm PECVD nitride hard mask. The polyimide/nitride stack was then etched to expose metal pads for probing. The second and third splits had no passivation [Figure 2(b)] and 1.2-μm TEOS passivation respectively [Figure 2(c)]. A fourth split, consisting of TEOS-gapfilled RIE metal (0.5-μm thick Ti/TiN/ Al(0.5%Cu)/Ti/ TiN stack) on 1.1 μm TEOS, was fabricated for a technology comparison [Figure 2(d)]. All wafers were annealed in forming gas at 390 °C for 30 min prior to electrical testing. Electrical Testing Intralevel leakage currents between the serpentine and comb ( comb1 + comb2 ) electrodes were measured in the 100 to 275 °C range using an HP4156A Precision Semiconductor Parameter Analyzer. With both comb and substrate grounded, a voltage ramp was applied to the serpentine to force current into the other electrodes via possible leakage paths indicated in Figure 3. As confirmed by capacitance-voltage measurements, positive V serp conditions ensured the Si surface remained in deep accumulation to behave essentially as a grounded plate during the I-V sweep. Since no potential difference existed between the comb and the substrate, the current returning to the comb electrode was measured to decouple parasitic leakage to the substrate. Electrical noise Figure 2. Cross-section of experimental splits: (a) polyimide-passivated inlaid Al(Cu), (b) unpassivated inlaid Al(Cu), (c) TEOS-passivated inlaid Al(Cu), and (d) TEOS-gapfilled RIE Al(Cu). nitride fluorinated polyimide